LINEAR INTEGRATED CIRCUITS 

                                                                         

LINEAR INTEGRATED CIRCUITS 

Course Objectives:

^Ø  Design of OPAMPS, Classification of OPAMPs.

^Ø   To study and design various linear applications of OPAMPs.

^Ø   To study and design various non linear applications of OPAMPs

Course Outcomes:

^Ø  Understand the basic building blocks of linear integrated circuits and its characteristics.

^Ø  Analyze the linear, non-linear and specialized applications of operational amplifiers.

^Ø  Understand the theory of ADC and DAC.

^Ø   Realize the importance of Operational Amplifier.

Sample and Hold Circuit

The sample and hold circuit, as its name implies samples an i/p signal and holds on to it last sampled value until the i/p is sampled again. Below fig shows a sample and hold circuit using an op-amp with an E- MOSFET. In this circuit the E-MOSFET works as a switch that is controlled by the sample and control voltage Vs, and the capacitor C serves as a storage element.

The analog signal Vin to be sampled is applied to the drain, and sample and hold control voltage Vs is applied to the gate of the E-MOSFET. During the positive portion of the Vs, the EMOSFET conducts and acts as a closed switch. This allows i/p voltage to charge capacitor C. In other words input voltage appears across C and in turn at the o/p as shown in above fig.2.9.On the other hand, when Vs is zero, the EMOSFET is off and acts as open switch. The only discharge path for C is, through the op-amp. However the i/p resistance of the op-amp voltage follower is also very high; hence the voltage across C is retained.

The time periods Ts of the sample-and-hold control voltage Vs during which the voltage across the capacitor is equal to the i/p voltage are called sample periods. The time periods TH of Vs during which the voltage across the capacitor is constant are called hold periods. The o/p of the op-amp is usually processed/ observed during hold periods. To obtain the close approximation of the i/p waveform, the frequency of the sample-and-hold control voltage must be significantly higher than that of the i/p.

                Fig.1.30: sample and hold circuit Fig 1.38 I/P and O/P wave forms